Conventionally, there has been proposed a technique for detecting, from a program subjected to optimization, an instruction stream which agrees with a predetermined pattern, and then replacing the instruction stream with another instruction stream determined correspondingly to the pattern. According to this technique, a program, for example, can be optimized by replacing a series of instructions, which realizes certain processing, with a single instruction which produces the same processing result as the certain processing. As an example of an instruction with which such a series of instructions is replaced, a TRT instruction in the S/390 architecture of IBM Corporation can be given.
The TRT instruction is an instruction for scanning a predetermined memory area sequentially from the beginning of the area, and for outputting an address or the like where a value satisfying a predetermined condition is stored. FIG. 15 is a control flow graph corresponding to processing performed by the TRT instruction. The processing performed by the TRT instruction corresponds to a series of processing of: reading out values stored in a memory area into a variable ch by looping through steps (1), (2), and (3) of each iteration of the loop sequentially from the beginning of the memory area bytearray with memory area index “i” being incremented by 1 at the end of each iteration in step (3) to reference the next sequential memory area location, namely bytearray [i], in step (1) of the next iteration; and terminating the processing via step (2) when a value of the variable ch satisfies any one of conditions cond1 to condN. A compiler can optimize a program by replacing the series of processing as described here with the single TRT instruction.
Reference documents are listed below. Non-patent Documents 1 and 2 will be referred to in embodiments.
However, a program subjected to optimization rarely agrees completely with a predetermined pattern. Conventionally, optimization has been given up in such a case. As a result, there are cases where an instruction uniquely supported by an architecture such as the TRT instruction cannot be effectively utilized.
Thus, there is a need for a program optimization that enables an architecture such as the TRT instruction to be effectively utilized.